This invention relates generally to ferroelectric memory circuits and, more particularly, to an improved sensing and writing scheme for use with ferroelectric memory cells.
A column 10 of a one-transistor, one-capacitor ("1T-1C") ferroelectric memory array circuit is shown in the simplified circuit diagram of FIG. 1. (The use of "column" and "row" designations is based upon conventions in the art, and does not necessarily correspond to the orientation shown in the drawing figures.) Although memory circuits typically include numerous columns for simplicity and clarity only one column 10 is shown in FIG. 1. Column 10 includes a sense amplifier 16 coupled to complementary bit lines 26 and 28. Bit line 26 (a first input of sense amplifier 16) is coupled to a column portion 14 of 1T-1C memory cells and has an associated bit line capacitance illustrated as capacitor 12. Bit line 28 (a reference input of sense amplifier 16,) is coupled to a reference cell 18. It will be appreciated by those skilled in the art that an actual column 10 is symmetrical with respect to sense amplifier 16, and that the schematic diagram of FIG. 1 represents a simplified electrical equivalent circuit. In practice, each bit line has an associated bit line, capacitance, attached memory cells, and a reference cell. Four 1T-1C ferroelectric memory cells 20 are shown within column portion 14 in FIG. 1, although any number can be used. Each memory cell 20 is representative of an entire row of memory cells (not shown) that span column 10. Each memory cell 20 includes an MOS access transistor 22 and a ferroelectric capacitor 24. The drain of access transistor 22 forms a data input/output node of each memory cell and is coupled to bit line 26. Each memory cell 20 is read from and written to by the action of a corresponding word line 30, and a corresponding plate line 32.
A column 40 of an alternative two-transistor, two-capacitor ("2T-2C") ferroelectric memory array circuit is shown in the simplified circuit diagram of FIG. 2. Column 40 includes a sense amplifier 48 coupled to complementary bit lines 52 and 54. Complementary bit lines 52 and 54 are coupled to a column portion 46 of 2T-2C memory cells. Each bit line has an associated bit line capacitance illustrated as capacitors 42 and 44. Since data is stored in a differential fashion in memory cells 50, column 40 does not include a reference cell. Four 2T-2C ferroelectric memory cells 50 representative of an entire row of memory cells are shown within column portion 46 in FIG. 2, although any number can be used. Referring now to FIG. 3, each memory cell 50 includes two MOS access transistors 60 and 62 and corresponding ferroelectric capacitors 64 and 66. The drain of access transistors 60 and 62 forms a complementary pair of data input/output nodes that are coupled to complementary bit lines 52 and 54. Each memory cell 50 is read from and written to by the action of a corresponding word line 56, and a corresponding plate line 58.
The operation of reading data from a ferroelectric memory cell, which resides in the non-volatile polarization of the ferroelectric capacitor and not the volatile quiescent stored voltage thereon, is described in U.S. Pat. No. 4,873,664 to Eaton. Jr. entitled "Self Restoring Ferroelectric Memory" and U.S. Pat. No. 4,888,733 to Mobley entitled "Non-volatile Memory Cell and Sensing Method", both of which patents are hereby incorporated by reference. An alternative method of reading data from a ferroelectric memory cell is described in a pending patent application Ser. No. 08/040,762 to Parris and Wilson, also assigned to Ramtron International Corporation and entitled "Ferroelectric Return to Zero Sensing Method", which is also hereby incorporated by reference. In each of these sensing methods, the ferroelectric capacitor is "poled" and charge is liberated that is stored in the capacitance associated with the bit line.
The bit line capacitance mentioned above in conjunction with the 1T-1C or 2T-2C memory circuits can either be the parasitic capacitance inherent in the bit line itself if a large number of memory cells are used in the memory array, or an additional integrated capacitance if the number of memory cells is small. In the latter case, the parasitic capacitance of the bit line is not sufficient to develop a voltage signal that can be sensed by the sense amplifier. In the present state of the art, this is true for ferroelectric memories. In FIG. 4, a graph is shown illustrating the relationship between the voltage signal developed at the bit line and the ratio of the memory cell capacitance to the bit line (digit line) capacitance. In FIG. 1, this is the ratio of capacitor 24 to capacitor 12. In FIG. 2, this is the ratio of capacitor 64 or 66 to capacitor 42 or 44. Note that no signal is developed if there is no bit line capacitance (ratio of infinity), and signal developed if there is no memory cell capacitance (ratio of zero). Between the two endpoints of the ratio axis, there exists some ideal ratio, for example one-to-three, where the bit line signal level is maximized. The ideal ratio will vary with the exact semiconductor process used, type of ferroelectric material used, number of memory cells, and word and plate line voltages used, among other factors, but it is currently believed that a ratio of about one is desirable. To achieve the optimum ratio that results in maximum bit line signal levels, an extrinsic capacitance is therefore needed in ferroelectric memories of relatively low density to supplement the parasitic capacitance of the bit line.
One problem with the additional bit line capacitance is that once fabricated, it is permanently connected to the bit line, which is in turn connected to the sense amplifier. This hardwire connection is shown in both FIG. 1 and FIG. 2. In the sensing operation of a ferroelectric memory, charge is transferred from the poled ferroelectric capacitor to the bit line. Once this is accomplished, the sense amplifier is activated to amplify the charge on the bit line and latch full logic levels. Since the extrinsic bit line capacitance is permanently connected to the sense amplifier and must be charge. when the bit line reaches full logic levels, the additional capacitance contributes to the operating current required, and creates transient current spikes that cause the power supply and ground lines to bounce. The larger the bit line capacitance needed for maximum signal levels, the worse the spiking and increase in operating current become. Alternatively, operating current can be maintained at a desirably low level, but at the expense of operating speed. Neither of these operating conditions is desirable.
What is desired is a method and circuit for eliminating the spiking and increased operating current caused by the necessary bit line capacitance during the active operation of the sense amplifiers a ferroelectric memory.